In order to reduce specific contact resistance at via/interconnect interface and to avoid device degradation with Cu diffusion into dielectrics, via cleaning technology is a critical issue for a scaled down Cu multilevel metallization.

S. Octopus

Publication type:Research Problem

Published:December 6, 2022

Language:English

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CC BY 4.0

DOI:

https://doi.org/10.57874/5x1p-tv18

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surface plasmon

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